Semiconductors are widely used in integrated circuits for electronic applications, including various information systems. Such integrated circuits typically use multiple bipolar junction transistors (BJT) and/or metal-oxide semiconductor field-effect transistors (MOSFET) fabricated in single-crystal silicon substrates. Many integrated circuits now require the introduction of dopants to one or more device junction layers for formation of the transistor device structures. There are several methods of introducing dopants to an integrated circuit surface, including epitaxial layer deposition with in-situ doping, chemical-vapor deposition (CVD) with in-situ doping, metal-organic chemical-vapor deposition (MOCVD) with in-situ doping, ion implantation, plasma-immersion ion implantation (PIII), and thermal gas-phase doping.
Several prior art references disclose methods of metal-organic chemical-vapor deposition (MOCVD) of semiconductor layers using organometallic precursors. U.S. Pat. No. 5,128,275 issued to Takikawa et al. discloses a method of growing a compound semiconductor layer by a metal-organic chemical-vapor deposition process. U.S. Pat. No. 5,015,747 issued to Hostalek et al. discloses the use of an organometallic compound for gas-phase deposition of metal on substrates. U.S. Pat. No. 5,300,185 issued to Hori et al. teaches a method of growing a III-V group compound semiconductor on a substrate by an MOCVD method. U.S. Pat. No. 4,830,982 issued to Dentai et al. discloses a method of forming epitaxial layers of Group III-V based semiconductor compounds produced by a MOCVD process through the use of organic titanium-based compounds. U.S. Pat. No. 4,504,331 issued to Kuech et al. describes an improved method of growing silicon doped gallium arsenide by MOCVD by adding a small amount of disilane to the gas-phase ambient. None of the above-mentioned prior art references discloses a method for gas-phase doping of a semiconductor layer.
U.S. Pat. No. 5,275,966 issued to Gedridge, Jr. discloses a low temperature CVD process for producing antimony-containing semiconductor materials using tri-isopropylantimony as the source of antimony. This method is not a gas-phase doping process since in-situ doping takes place during a material layer deposition process.
U.S. Pat. No. 5,242,859 issued to Degelormo et al. is directed to a method of doping a semiconductor surface with the use of an oxidizing agent.
U.S. Pat. Nos. 4,988,640 and 4,904,616, both issued to Bohling et al., describe methods of using fluorinated organometallic compounds, particularly arsine, antimony and phosphine substitutes, for in-situ doping during epitaxial growth, ion implantation, and diffusion doping.
U.S. Pat. No. 4,618,381 issued to Sato et al. discloses a doping method of adding impurities to a semiconductor base material in a vacuum chamber using a glow discharge (plasma excitation) at less than 400.degree. C. This is otherwise known in the industry as a Plasma Immersion Ion Implantation (PIII) process, and is a type of ion implantation using low-energy ions.